1. Field of the Invention
The present invention relates to a demodulator for used with a wireless communication receiver, in particular, to a demodulator having a DC offset controller that controls a frequency offset with an angle signal and an error signal.
2. Description of the Related Art
In recent years, digital wireless communication systems using microwaves and ultra-microwaves have been widely used along with analog wireless communication systems. In particular, mobile wireless communication systems such as portable telephone system and PHS (Persona Handyphone System) have been actively developed and invested as an infrastructure of digital communication lines.
In a demodulator of a digital wireless communication system, a frequency offset has been controlled so as to suppress data errors and accurately demodulate data. FIG. 11 is a block diagram showing the structure of a demodulator for use with a conventional digital wireless communication system. In FIG. 11, the demodulator comprises multiplying units 1 and 2, an oscillator 5, A/D converters 3 and 4, a complex multiplying unit 6, a phase detector 7, an LPF 8, an NCO (Numerical Controlled Oscillator) 9, a DC offset controller 11, and a Π/2 shifter 12.
In a receiver of a digital wireless communication system, a received radio signal is down-converted into a desired IF signal. The resultant IF signal is supplied to the demodulator as shown in FIG. 11. The detecting method of the demodulator is for example quasi-synchronous detecting method. The input modulated signal is an orthogonally modulated signal corresponding to QPSK method or QAM method. Orthogonal components (channels) of the modulated signal are denoted by Ich (In-Phase Channel) and Qch (Quadri-Phase Channel).
The oscillator 5 is a local oscillator with the same frequency as that of the input IF signal. An output signal of the oscillator 5 and a signal of which the phase of the output signal of the oscillator 5 is shifted for Π/2 by the Π/2 shifter 12 are multiplies by the IF signal of the IF-IN. Thus, signal components I and Q that are base band signals of the signals Ich and Qch are obtained. The signal components I and Q are supplied to the A/D converters 3 and 4, respectively. The A/D converters 3 and 4 convert the signal components I and Q into digital signals I1 and Q1, respectively. Since the demodulator performs the quasi-synchronous detection, the digital signals I1 and Q1 are not perfect base band signals. Instead, the digital signals I1 and Q1 contain carrier frequencies.
The DC offset controller 11 inputs the digital signals I1 and Q1, removes DC offset components from the digital signals I1 and Q1, and outputs signals I2 and Q2.
The complex multiplying unit 6 inputs the signals I2 and Q2, removes carrier frequencies from the signals I2 and Q2 using rotation angle information sin and cos that are input from the NCO 9, and outputs resultant signals Ich4 and Qch4.
The phase detector 7 inputs the signals Ich4 and Qch4 from the complex multiplying unit 6 and outputs a phase error signal Pd1. The phase error signal Pd1 is supplied to the LPF 8. The LPF 8 smooths the phase error signal Pd1 and outputs the resultant phase error signal Pd2 to the NCO 9.
The NCO 9 converts the phase error signal Pd2 that is input from the LPF 8 into rotation angle signals sin and cos.
The output signals Ich4 and Qch4 of the complex multiplying unit 6 are converted into a serial signal. Thus, original digital data can be obtained.
Next, another structure of the DC offset controller 11 will be described. In the structure, the DC offset controller 11 controls a DC offset with information other than error information that is output from the complex multiplying unit 6.
FIG. 7 shows an influence of a DC offset upstream of the complex multiplying unit that compensates a frequency/phase offset. In FIG. 7, a polarity determining unit 121 determines the polarities of digital signals Ich1 and Qch1. An adding unit 123 adds the output signals of the polarity determining unit 121 with an output signal of the adding unit 123. A flip-flop F/F 122 temporarily stores an output signal of the adding unit 123. Corresponding to the stored polarity, the polarity determining unit 121 determines whether or not a DC offset is present.
FIG. 12 shows an influence of a DC offset upstream of the complex multiplying unit 6 that compensates a frequency/phase offset in a modulating method of which signal points are present on a concentric circle. Dots on the circle represent signals in the case that DC offset components are present on both Ich and Qch. Since the frequence/phase offset has not been compensated, the signals are offset to the origin of the coordinates. When the DC offset is removed from the signals, the resultant signals are represented as a solid circle whose center is at the origin of the coordinates.
FIG. 13 shows a signal on only Qch (or Ich) in the case that the signal has a DC offset. The signal reciprocally moves on a straight line. The signal deviates to the axis I. In FIG. 13, the probability of which the value on Qxe2x80x2ch is positive is higher than the probability of which the value on Qxe2x80x2ch is negative. When the DC offset is removed from the signal, the resultant signal distributes symmetrically to the axis I as denoted by a solid line Qch.
FIG. 14 is a block diagram showing an example of the structure of the conventional DC offset controller 11. In FIG. 14, the DC offset controller 11 comprises adding units 111 and 112 and LPFs 113 and 114. In the DC offset controllers 11, the adding units 111 and 112 remove low band components including DC components that are output components of the LPFs 113 and 114 and output signals Ich2 and Qch2 of which DC offset components are removed.
In the conventional structure, although error information is not obtained, when DC offset components are present, since the probability of which each of signals Ich and Qch is positive is different from the probability of which each of signals Ich and Qch is negative, the DC offset components can be controlled corresponding to polarity signals on Ich and Qch. Since the polarity signals are used as control signals, LPFs shown in FIG. 7 or 9 are used. When an input signal is positive, a subtracting operation or a count-down operation is performed. When an input signal is negative, an adding operation or a count-up operation is performed. Thus, the probability of which each signal is positive becomes the same as the probability of which each signal is negative. Thus, the DC offset components are removed.
However, as described above, in the conventional structure, although DC offset components can be removed, since only polarities as control information are used, the DC offset control becomes coarse.
As denoted by I-Q coordinates shown in FIG. 15, when signals that are output from the complex multiplying unit 6 contain DC offset components, the signals are denoted as circles with radiuses of DC offset components. FIG. 15 shows signals in the QPSK modulating method. Likewise, in other modulating methods, signals are denoted as circles with centers of correct signal points. Thus, when the distance between signal points is short, the signals are easily affected by noise and thereby the error rate characteristics deteriorate.
In particular, when a signal is transmitted with many value data for a large capacity of a communication line, due to a DC offset, the distance between signal points further shortens. Thus, the error rate characteristics remarkably deteriorate.
An object of the present invention is to provide a demodulator for accurately removing a DC offset so as to more suppress deterioration of error rate characteristics than conventional demodulators in the case that a modulating method with many-value data and short signal distance is used.
A first aspect of the present invention is a demodulator for use with a digital wireless communication system, comprising a DC offset controller for removing a DC offset of a modulated signal that is input to the demodulator, a complex multiplying unit for complex-multiplying an output signal of the DC offset controller, a phase detector for detecting an amplitude error signal and a phase error signal from an output signal of the complex multiplying unit, an LPF (low pass filter) for outputting a low band component of the phase error signal, and an NCO (numerical controlled oscillator) for converting an output signal of the LPF into a sin component and a cos component that have orthogonal relation, wherein the sin component and the cos component are input to the complex multiplying unit, and wherein the amplitude error signal, the sin component, and the cos component are input to the DC offset controller.
The phase detector multiplies and adds an output signal of the complex multiplying unit and the amplitude error signal that is output from the error detector and obtains the phase error signal.
The DC offset controller multiplies the amplitude error signal by the sin component, multiplies the amplitude error signal by the cos component, adds one of the multiplied results and the other of the multiplied results, subtracts one of the multiplied results from the other of the multiplied results, extracts low band components of the added result and the subtracted result through the LPF, adds or subtracts the low band components to/from the orthogonal modulated signal component, and outputs the result as an orthogonal modulated signal component.
A second aspect of the present invention is a digital wireless communication receiver having a demodulator for demodulating transmitted digital data, wherein the demodulator is the demodulator of the first aspect.
These and other objects, features and advantages of the present invention will become more apparent in light of the following detailed description of a best mode embodiment thereof, as illustrated in the accompanying drawings.